Extending Hardware Transactional Memory Capacity via Rollback-Only Transactions and Suspend/Resume

Transactional memory, which aims at simplifying concurrent programming by bringing the familiar abstraction of transactions to parallel computing, has grown from a “research toy” to a mature technology integrated in mainstream programming language and CPU architectures. Yet, despite being supported in commodity processors from Intel and IBM, hardware transactional memory (HTM) suffers from some limitations that hamper its wide adoption. One such notable limitation is the inability to execute transactions whose working sets exceed the capacity of CPU caches. In this paper we propose a novel approach to mitigating this limitation on IBM’s POWER8 architecture by leveraging a key combination of techniques: uninstrumented read-only transactions, ROT-based update transactions, HTM-friendly (software-based) read-set tracking, and self-tuning. Our algorithm, P8TM, can dynamically switch between different execution modes to best adapt to the nature of the transactions and the experienced abort patterns. In-depth evaluation with several benchmarks indicates that P8TM can achieve striking performance gains in workloads that stress the capacity limitations of HTM, while achieving performance on par with HTM even in unfavourable workloads.